datasheet pecl/cmos to cmos clock driver ics558-01 idt? / ics? pecl/cmos to cmos clock driver 1 ics558-01 rev f 051310 description the ics558-01 accepts a high speed input of either pecl or cmos, integrates a divider of 1, 2, 3, or 4, and provides four cmos low skew outputs. the chip also has output enables so that one, three, or all four outputs can be tri-stated. the ics558-01 is a member of the idt clock blocks? family of clock generation, synchronization, and distribution devices. features ? 16-pin tssop package ? pb (lead) free package ? selectable pecl or cmos inputs ? operates up to 250 mhz ? works as a voltage translator ? four low skew (<250 ps) outputs ? selectable internal divider ? operating input voltages of 3.3 v or 5.0 v ? operating output voltages of 2.5 v, 3.3 v or 5.0 v ? ideal for ia64 designs block diagram oe1 clk1 clk2 clk3 clk4 peclin output divide peclin s0, s1 gnd vddp oe0 gnd vddc 2 1 0 cmosin selpecl
ics558-01 pecl/cmos to cmos clo ck driver pecl clock driver idt? / ics? pecl/cmos to cmos clock driver 2 ics558-01 rev f 051310 pin assignment input clock selection tri-state table output divide selection pin descriptions 12 1 11 2 10 3 9 s0 4 s1 5 vddp 6 vddc 7 peclin 8 peclin clk1 clk2 clk3 gnd clk4 oe1 cmosin gnd 16 15 14 13 oe0 selpecl 16-pin 173 mil (0.65mm) tssop selpecl input 0cmosin 1 peclin oe1 oe0 clk 1 clk 2, 3, 4 0 0 tri-state tri-state 0 1 clock on tri-state 1 0 tri-state clock on 1 1 clock on clock on s1 s0 output divide 00 /1 01 /2 10 /3 11 /4 pin number pin name pin type pin description 1 s0 input select 0 for output divider. see table above. internal pull-up to vddp. 2 s1 input select 1 for output divider. see table above. internal pull-up to vddp. 3 vddp power connect to +3.3 v or +5 v. decouple to pin 6. 4 peclin clock input pecl input. connect to ground if not used. 5 peclin clock input complimentary pecl input. connect to ground if not used. 6 gnd power connect to ground. 7 cmosin clock input cmos input. connect to ground if not used. 8 oe0 input output enable 0. see table above. internal pull-up to vddp. 9 oe1 input output enable 1. see table above. internal pull-up to vddp. 10 gnd power connect to ground. 11 clk4 output low skew clock output. 12 clk3 output low skew clock output. 13 clk2 output low skew clock output. 14 clk1 output low skew clock output. 15 vddc power connect to +2.5 v, +3.3 v, or +5 v. decouple to pin 10. 16 selpecl input selects pecl or cmos input. see table above. internal pull-up to vddp.
ics558-01 pecl/cmos to cmos clo ck driver pecl clock driver idt? / ics? pecl/cmos to cmos clock driver 3 ics558-01 rev f 051310 external components the ics558-01 requires two 0.01 f capacitors between vddp and gnd, and vddc and gnd?one on each side of the chip. these must be close to the chip to minimize lead inductance. series termination resistors of 33 ? can be used on the outputs (these also must be close to the chip). absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics558-01. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. dc electrical characteristics vddp = vddc = 3.3v (unless stated otherwise), ambient temperature 0 to +70 c item rating supply voltage; vddp, vddc (referenced to ground) 7.0 v inputs and clock outputs (referenced to ground) -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c soldering temperature (maximum of 10 seconds) 260 c parameter symbol conditions min. typ. max. units operating voltage, vddp vddp vddc 3.0 5.5 v operating voltage, vddc vddp vddc 2.375 vddp v input high voltage, cmosin v ih (vddp/2)+ 1 v input low voltage, cmosin v il (vddp/2)- 1 v input high voltage v ih non-clock pins vddp-0.5 vddp v input low voltage v il non-clock pins 0.5 v common mode range, peclin vddp=5 v vddp-3.7 vddp-0.6 v common mode range, peclin vddp=3.3 v vddp-2.0 vddp-0.6 v peak-to-peak input voltage, peclin 0.3 1.0 v output high voltage v oh vddc = 5 v, i oh = -24 ma vddc-0.4 v output low voltage v ol vddc = 5 v, i ol = 24 ma 0.4 v output high voltage v oh vddc = 3.3 v, i oh = -18 ma vddc-0.4 v output low voltage v ol vddc = 3.3 v, i ol = 18 ma 0.4 v
ics558-01 pecl/cmos to cmos clo ck driver pecl clock driver idt? / ics? pecl/cmos to cmos clock driver 4 ics558-01 rev f 051310 ac electrical characteristics vddp = vddc = 3.3 v (unless stated otherwise), ambient temperature 0 to +70 c thermal characteristics (16-pin tssop) output high voltage v oh vddc = 2.5 v, i oh = -8 ma vddc-0.4 v output low voltage v ol vddc = 2.5 v i ol = 8 ma 0.4 v operating supply current iddp no load, 100 mhz input 22 ma operating supply current iddc no load, 100 mhz input 18 ma short circuit current +70 ma on-chip pull-up resistor r pu 250 k ? input capacitance c in 4pf parameter symbol conditions min. typ. max. units input frequency 0 250 mhz output rise time t or 800 ps output fall time t of 750 ps skew, between any output clocks (assumes identically loaded outputs with identical rise times, measured at vddc/2) 0 250 ps propagation delay /1 5.0 ns /2 6.0 ns /3 ns /4 7.0 ns output clock duty cycle for /2 and /4 45 50 55 % output clock duty cycle for /1 and /3 45 50 55 % parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w parameter symbol conditions min. typ. max. units
ics558-01 pecl/cmos to cmos clo ck driver pecl clock driver idt? / ics? pecl/cmos to cmos clock driver 5 ics558-01 rev f 051310 package outline and package dimensions (16-pin tssop, 4.40 mm body, 0.65 mm pitch) package dimensions are kept current with jedec publication no. 95, mo-153 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 558G-01LF 558G-01LF tubes 16-pin tssop 0 to +70 c 558G-01LFt 558G-01LF tape and reel 16-pin tssop 0 to +70 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 a0 8 0 8 aaa -- 0.10 -- 0.004
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